Advanced VLSI Design and Testability Issues

This book facilitates the VLSI-interested individuals with not only in-depth knowledge but also the broad aspects of it by explaining its applications in different fields including image processing and biomedical. The deep understanding of basic concepts gives you the power to develop a new application aspect which is very well taken care of in this book by using simple language in explaining the concepts. In the VLSI world the importance of hardware description languages cannot be ignored as the designing of such dense and complex circuits is not possible without them. Both Verilog and VHDL languages are used here for designing. The current needs of high-performance integrated circuits (ICs) including low power devices and new emerging materials which can play a very important role in achieving new functionalities are the most interesting part of the book. The testing of VLSI circuits becomes more crucial than the designing of the circuits in this nanometer technology era. The role of fault simulation algorithms is very well explained and its implementation using Verilog is the key aspect of this book. This book is well organized into 20 chapters. Chapter 1 emphasizes on uses of FPGA on various image processing and biomedical applications. Then the descriptions enlighten the basic understanding of digital design from the perspective of HDL in Chapters 2â5. The performance enhancement with alternate material or geometry for silicon-based FET designs is focused in Chapters 6 and 7. Chapters 8 and 9 describe the study of bimolecular interactions with biosensing FETs. Chapters 10â13 deal with advanced FET structures available in various shapes materials such as nanowire HFET and their comparison in terms of device performance metrics calculation. Chapters 14â18 describe different application-specific VLSI design techniques and challenges for analog and digital circuit designs. Chapter 19 explains the VLSI testability issues with the description of simulation and its categorization into logic and fault simulation for test pattern generation using Verilog HDL. Chapter 20 deals with a secured VLSI design with hardware obfuscation by hiding the ICâs structure and function which makes it much more difficult to reverse engineer. . Language: English